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Ordering number : ENN6201A
Monolithic Digital IC
LB1876
Three-Phase Brushless Motor Driver for Polygon Mirror Motors
Overview
The LB1876 is a driver for polygon mirror motors such as used in laser printers and similar equipment. It incorporates all necessary circuitry (speed control + driver) on a single chip. Direct PWM drive enables drive with low power loss.
Package Dimensions
unit: mm 3235A-HSOP36
[LB1876]
0.65 (4.9) 0.25 0.8 2.0 0.3 17.8 (6.2) 2.7
Functions and Features
Three-phase bipolar drive Direct PWM drive technique Built-in lower side output diode Output current limiter Reference clock input circuit (FG frequency equivalent) PLL speed control circuit Phase lock detector output (with masking function) Built-in protection circuitry includes current limiter, restraint protection, overheat protection, low-voltage protection, etc. * Brake method switching circuit (free-run or reverse torque) * 5V regulator output * Power save function * * * * * * * *
7.9
36
1
(0.5) (2.25)
2.45max
0.1
SANYO: HSOP36
Specifications
Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage 1 Maximum output current Allowable power dissipation 1 Allowable power dissipation 2 Operating temperature Storage temperature * Substrate: 114.3 x 76.1 x 1.6 mm3, glass epoxy Symbol VCC max IO max Pd max1 Pd max2 Topr Tstg T 500 ms IC only *With substrate Conditions Ratings 30 2.5 0.9 2.1 -20 to +80 -55 to +150 Unit V A W W C C
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
61202RM (OT)/62599RM (KI) No. 6201-1/14
10.5
LB1876 Allowable Operating Ranges at Ta = 25C
Parameter Power supply voltage range 5 V regulated output current LD pin voltage LD pin output current FGS pin voltage FGS pin output current Symbol VCC IREG VLD ILD VFGS IFGS Conditions Ratings 9.5 to 28 0 to -20 0 to 28 0 to 15 0 to 28 0 to 10 Unit V mA V mA V mA
Electrical Characteristics at Ta = 25C, VCC = VM = 24 V
Parameter Power supply current 1 Power supply current 2 [5V regulated output] Output voltage Voltage fluctuation Load fluctuation Temperature coefficcient [Output block] Output saturation voltage 1 Output saturation voltage 2 Output leak current Lower side diode forward voltage 1 Lower side diode forward voltage 2 [Hall amplifier block] Input bias current Common mode input voltage range Hall input sensitivity Hysteresis width Input voltage L H Input voltage H L [FG/Schmitt block] Input bias current Common mode input voltage range Input sensitivity Hysteresis width Input voltage L H Input voltage H L [PWM oscillator] Output High level voltage Output Low level voltage External capacitor charge current Oscillator frequency Amplitude [FGS output] Output saturation voltage Output leak current [CSD oscillator] Output High level voltage Output Low level voltage Amplitude External capacitor charge current External capacitor discharge current Oscillator frequency VOH(CSD) VOL(CSD) V(CSD) ICHG1 ICHG2 f(CSD) C = 0.068 F 2.65 0.75 1.75 -13.5 5.5 3.0 0.9 2.1 -9 9 30 3.3 1.1 2.3 -5.5 13.5 V V Vp-p A A Hz VOL(FGS) IFGS = 7 mA IL(FGS) 0.15 0.5 10 V A VOH(PWM) VOL(PWM) ICHG f(PWM) V(PWM) VPWM = 2 V C = 3000 pF 1.05 2.5 1.2 -125 2.8 1.5 -95 22 1.27 1.50 3.1 1.8 -75 V V A kHz Vp-p IB(FGS) VICM(FGS) VIN(FGS) VIN(FGS) VSLH(FGS) VSHL(FGS) -2 0 80 15 24 12 -12 42 -0.5 VREG - 2.0 A V mVp-p mV mV mV VIN(HA) VSLH VSHL IHB VICM -2 0 80 15 24 12 -12 42 -0.5 VREG - 2.0 A V mVp-p mV mV mV VOsat1 VOsat2 IOleak VD1 VD2 ID = -1.0 A ID = -2.0 A 1.2 1.5 IO = 1.0 A, VO(SINK)+VO(SOURCE) IO = 2.0 A, VO(SINK)+VO(SOURCE) 2.0 2.6 2.5 3.2 100 1.5 1.9 V V A V V VREG VREG1 VREG2 VREG3 VCC = 9.5 to 28 V IO = -5 to -20 mA Design target value 4.65 5.0 50 30 0 5.35 100 100 V mV mV mV/C Symbol ICC 1 ICC 2 Quiescent Current Conditions Ratings min typ 17 3.6 max 22 5.0 Unit mA mA
Continued on next page.
No. 6201-2/14
LB1876
Continued from preceding page.
Parameter [Phase comparator output] Output High level voltage Output Low level voltage Output source current Output sink current [Phase lock detector output] Output saturation voltage Output leak current [ERR amplifier] Input offset voltage Input bias current Ouput High level voltage Ouput Low level voltage DC bias level [Current limiter] Drive gain 1 Drive gain 2 Limiter voltage [Thermal shutdown operation] Termal shutdown operating temperature Hysteresis width [Low voltage protection] Operating voltage Hysteresis [CLD circuit] External capacitor charge current Operating voltage [CLK pin] External input frequency High level input voltage Low level input voltage Input open voltage Hysteresis width High level input current Low level input current [S/S pin] High level input voltage Low level input voltage Input open voltage Hysteresis width High level input current Low level input current [LDSEL pin] High level input voltage Low level input voltage Input open voltage High level input current Low level input current [BRSEL pin] High level input voltage Low level input voltage Input open voltage High level input current Low level input current VIH(BRSEL) VIL(BRSEL) VIO(BRSEL) IIH(BRSEL) VLDSEL = VREG IIL(BRSEL) VLDSEL = 0 V 3.5 0 VREG-0.5 -10 -280 0 -210 VREG 1.5 VREG 10 V V V A A VIH(LDSEL) VIL(LDSEL) VIO(LDSEL) IIH(LDSEL) VLDSEL = VREG IIL(LDSEL) VLDSEL = 0 V 3.5 0 VREG-0.5 -10 -280 0 -210 VREG 1.5 VREG 10 V V V A A VIH(SS) VIL(SS) VIO(SS) VIS(SS) IIH(SS) IIL(SS) VS/S = VREG VS/S = 0 V 3.5 0 VREG-0.5 0.35 -10 -280 0.5 0 -210 VREG 1.5 VREG 0.65 +10 V V V V A A fI(CKIN) VIH(CKIN) VIL(CKIN) VIO(CKIN) VIS(CKIN) IIH(CKIN) VCKIN = VREG IIL(CKIN) VCKIN = 0 V 0.1 3.5 0 VREG-0.5 0.35 -10 -280 0.5 0 -210 10 VREG 1.5 VREG 0.65 +10 kHz V V V V A A ICLD VH(CLD) -6 3.25 -4.3 3.5 -3 3.75 V V VSD VSD 8.1 0.2 8.5 0.35 8.9 0.5 V V TSD TSD Design target value (junction temperature) Design target value (junction temperature) 150 180 40 C C GDF1 GDF2 VRF in phase lock mode in unlock mode VCC - VM 0.4 0.8 0.45 0.5 1.0 0.5 0.6 1.2 0.55 times times V VIO(ER) IB(ER) VOH(ER) VOL(ER) VB(ER) IOH = -500 A IOL = 500 A -5% Design target value -10 -1 VREG-1.2 VREG-0.9 0.9 VREG/2 1.2 +5% +10 +1 mV A V V V VOL(LD) IL(LD) ILD = 10 mA VO = VCC 0.15 0.5 10 V A VPDH VPDL IPD+ IPD- IOH = -100 A IOH = 100 A VPD = VREG/2 VPD = VREG/2 1.5 VREG-0.2 VREG-0.1 0.2 0.3 -0.5 V V mA mA Symbol Conditions Ratings min typ max Unit
No. 6201-3/14
LB1876 Three-phase logic truth table (IN = "H" indicates the IN+ > IN- condition)
IN1 H H H L L L IN2 L L H H H L IN3 H L L L H H OUT1 L L M H H M OUT2 H M L L M H OUT3 M H H M L L
Pin Assignment
VREG
FRAME
BRSEL
OUT3
GND3
LDSEL
VCC
VM2
CLD
LD
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
EI
20
19
LB1876
TOC
VM1
CLK
S/S
FGS
EO
NC
PD
Top view
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
GND1
FGIN+
GND2
OUT2
OUT1
2.4
With substrate (114.3 x 76.1 x 1.6 mm3, glass epoxy) Power dissipation, Pd max -- W
2.1 2.0
1.6
FRAME
Pd max -- Ta
FGIN-
1.2
1.18
IC independent
0.9 0.8
0.4
0 -20
0
20
40
60
80
100
Ambient temperature, Ta -- C
FGFIL
PWM
IN3+
IN2+
IN3-
IN1+
IN2-
IN1-
CSD
NC
PH
FC
No. 6201-4/14
LB1876 Pin Description
Pin name OUT1 OUT2 OUT3 IN1+, IN1- IN2+, IN2- IN3+, IN3- FG IN+ FG IN- GND1 GND2 PWM FC FGFIL Pin number 2 1 36 8, 9 6, 7 4, 5 10 11 12 13 14 15 16 FG comparator non-inverting input. FG comparator inverting input. Control circuit ground. Sub-ground. PWM oscillation frequency setting pin. Connect to ground via capacitor. Current control circuit frequency characteristics compensation pin. Connect to ground via capacitor. FG filter pin. Connect to ground via capacitor if noise in FG signal is a problem. Restraint protection circuit operating time setting pin/reset pulse setting pin. Connect to ground via capacitor. If the protection circuit is not to be used, connect a resistor in parallel with capacitor. RF waveform smoothing pin. Connect to ground via capacitor. Torque specifying input pin. Normally connected to EO pin. When TOC potential falls, ON duty cycle ratio of lower side output transistors changes and torque increases. Error amplifier output. Error amplifier input. Phase comparator output pin. Phase deviation is output as a duty cycle change of the pulse. Phase lock signal masking time setting pin. Connect to ground via capacitor. Leave open if masking is not required. FG Schmitt output (open collector output). Phase lock detector output (open collector output). Goes ON when PLL is locked. Start/stop input. Low: Start; High or Open: Stop. Clock input. 10 kHz max. Output block power supply. Short to VM2 for use. Output current detector pin. Connect to VCC via low resistor. Set to maximum output current IOUT = 0.5/Rf. Power supply pin. Connect to ground via capacitor to prevent noise. 5V regulator output pin (control circuit power supply). Connect to ground via capacitor to stabilize operation. Phase lock signal masking switching pin. When "Low", the unlock signal (short "High" signal of LD output) is masked. When "High" or Open, the lock signal (short "Low" signal of LD output) is masked. Braking method select pin. "Low" selects reverse torque control and "High" or Open selects free-run. When reverse torque is controlled, lower side output transistors require external SBD. Output circuit ground. The FRAME pin is connected internally to the metal frame at the base of the IC. Electrically, both the FRAME pin and the metal frame are left open. To improve thermal dissipation, provide a corresponding land on the PCB and solder the FRAME pin to that land. Not connected internally. Can be used for wiring. Hall input pins for each phase. Logic High indicates VIN+ > VIN-. Function Output pins. PWM controls duty cycle ratio by lower transistors. Connect Schottky diode between these pins and VCC.
CSD
17
PH TOC EO EI PD CLD FGS LD S/S CLK VM1 VM2 VCC VREG LDSEL
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
BRSEL GND3
33 34
FRAME
--
NC
3, 35
No. 6201-5/14
LB1876 Equivalent Circuit Block Diagram and Sample Application Circuit
VREG VREG
FGFIL
FGS
LD
LDSEL
CLD PD
FGI NFGI N+
LDSEL
- +
FG FI LTER
LD VREG
- +
EI
EO
CLK
CLK
PLL TSD VREG
TOC VREG
PWM
PWM OSC S/S
COMP
CONT AMP PEAK HOLD CURR LIM
FC
S/S
PH VCC Rf
BRSEL
VCC VM2 VM1
BRSEL
LOGIC
CSD
SD OSC
COUNT HALL LOGIC DRI VER HA LL HYS AMP
OUT1
OUT2
OUT3
IN1+ IN1- IN2+ IN2- IN3+ IN3- GND1 GND2 VREG
GND3
Top view
No. 6201-6/14
LB1876 Pin Descriptions
Pin No. 2 1 36 Symbol OUT1 OUT2 OUT3 Description Motor drive output. Connect Schottky diodes between the outputs and VCC. Equivalent circuit
VCC 300
VM2
29 28
VM1
GND3 Output block ground
34
Output block power supply and output current detection 28 29 VM1 VM2 Connect low-resistance resistors Rf between these pins and VCC. The output current is limited to the current value set by IOUT = VREF/Rf.
1
2
36
34
3 35
NC NC
Since these are not connected internally, they can be used for wiring.
VREG
8 9 6 7 4 5
IN1+ IN1- IN2+ IN2- IN3+ IN3-
Hall device inputs These inputs return a high level when IN+ > IN- and a low level when IN- > IN+. A Hall signal amplitude of at least 100 mV p-p (differential) is desirable. Insert a capacitor between IN+ and IN- if noise on the Hall signal is a problem.
4
6
8
300
300
5
7
9
VREG
FG inputs 10 11 FGIN1+ FGIN1- If noise on the FG signal is a problem, insert either a capacitor or a filter consisting of a capacitor and a resistor.
10
300
300
11
12 13
GND1 GND2
Control circuit block ground Sub-ground
Continued on next page.
No. 6201-7/14
LB1876
Continued from preceding page.
Pin No. Symbol Description Equivalent circuit
VREG
Sets the PWM oscillator frequency. 14 PWM Connect a capacitor between this pin and ground. A capacitance of 1800 pF for C sets the frequency to approximately 37 kHz.
200 2K
14
VREG
Current control circuit frequency characteristics correction. 15 FC Insert a capacitor (on the order of 0.01 to 0.1 F) between this pin and ground. The output duty is determined by the ratio of the voltage on this pin and the PWM oscillator waveform.
300
15
VREG
FG filter connection 16 FGFIL If noise on the FG signal is a problem, insert a capacitor (under about 2200 pF) between this pin and ground.
16
VREG
Sets the operating time of the constraint protection circuit and also sets the initial reset pulse. 17 CSD A protection operating time of about 8 seconds can be set by connecting a capacitor (about 0.068 F) between this pin and ground. If the protection circuit is not used, connect a capacitor and resistor (about 4700 pF, 220 k) in parallel between this pin and ground.
300
17
VREG
RF smoothing 18 PH If noise on the RF signal is a problem, insert a capacitor between this pin and ground.
500
18
Continued on next page.
No. 6201-8/14
LB1876
Continued from preceding page.
Pin No. Symbol Description Equivalent circuit
VREG
Torque command voltage input 19 TOC Normally, this pin is connected to the EO pin. When the TOC voltage falls, the on duty of the lower side transistor increases.
300
19
VREG
20
EO
Error amplifier output
20
40k
VREG
21
EI
Error amplifier input
300
21
VREG
Phase comparator output 22 PD The phase error is converted to a pulse duty and output from this pin.
300 22
VREG
Phase lock signal mask time setting 23 CLD A mask time of about 90 ms can be set by inserting a capacitor (about 0.1 F) between this pin and ground. Leave this pin open if there is no need to mask.
300
23
Continued on next page.
No. 6201-9/14
LB1876
Continued from preceding page.
Pin No. Symbol Description Equivalent circuit
VREG
24
24 FGS FG Schmitt output
VREG
Phase lock detection output 25 LD Turns on (goes low) when phase lock is detected.
25
VREG
Start/stop control Low: 0 to 1.5 V 26 S/S High: 3.5 V to VREG Hysteresis: About 0.5 V Apply a low level to start; this pin goes high when open.
22k 2k
26
VREG
Clock input Low: 0 to 1.5 V High: 3.5 V to VREG 27 CLK Hysteresis: About 0.5 V fCLK = 10 kHz maximum If there is noise on the clock signal, remove that noise with a capacitor.
22 k 2k
27
Power supply 30 VCC Insert a capacitor between this pin and ground to prevent noise from entering the IC. (Use a value of 20 or 30 F or higher.)
VCC
Stabilized power supply output (5 V output) 31 VREG Insert a capacitor between this pin and ground for stabilization. (About 0.1 F.)
31
Continued on next page. No. 6201-10/14
LB1876
Continued from preceding page.
Pin No. Symbol Description Equivalent circuit
VREG
Phase lock signal mask switching Low: 0 to 1.5 V High: 3.5 V to VREG 32 LDSEL When open, this pin goes to the high level. When low, transient unlock signals (short high-level periods on the LD output) are masked, and when high, transient lock signals (short low-level periods on the LD output) are masked.
30 k 2k
32
VREG
Braking control Low: 0 to 1.5 V High: 3.5 V to VREG 33 BRSEL When open, this pin goes to the high level. When low, reverse torque control is applied and when high, the circuit operates in freerunning mode. An external Schottky barrier diode is required on the low side output when reverse torque control is applied.
30 k 2k
33
FREME
This pin must be left open.
No. 6201-11/14
LB1876 LB1876 Overview 1. Speed control circuit This IC provides high-precision, low-jitter, and stable motor rotation since it adopts a PLL speed control technique. This PLL circuit compares the phases of the edges on the CLK signal (falling edges) and the FG signal (falling edges on the FGIN+.FGS output) and controls the speed using that error output. The FG servo frequency during control operation is the same as the clock frequency. fFG(servo) = fCLK 2. Output drive circuit To reduce power loss in the output, this IC adopts a direct PWM drive technique. The output transistors are always saturated when on, and the motor drive power is controlled by changing the output on duty. Since the lower side transistor is used for the output PWM switching, Schottky diodes must be inserted between the outputs and VCC. (This is because if the diodes used do not have a short reverse recovery time, instantaneous through currents will flow when the lower side transistor turns on.) The diodes between the outputs and ground are built in. However, if problems (such as waveform disruption during lower side kickback) occur for large output currents, attach external rectifying diodes or Schottky diodes. If reverse control mode is selected for braking and problems such as incorrect operation or excess heat generation due to the reverse recovery time of the lower side diode causes a problem, add an external Schottky diode. 3. Current control circuit The current control circuit controls the current (limits the peak current) to the current determined by I = VRF/Rf (VRF = 0.5 V typ., Rf: current detection resistor). The limiting operation consists of reducing the output on duty to suppress the current. The current control circuit detects the diode reverse recovery current due to the PWM operation, and has an operating delay (about 3 s) to prevent incorrect current limiting operation. If the motor coils have a relatively low resistance, or relatively low inductance, the changes in current flow at startup (the state where the motor presents no back electromotive force) will be rapid. As a result, the current limiter may operate at currents in excess of the set current due to this delay. In such cases, the current limit value must be set so as to take the current increase due to the delay into account. 4. Power saving circuit This IC goes to the power saving state, which reduces power consumption, in the stopped state. Power is reduced in the power saving state by cutting the bias current to most of the circuit blocks in the IC. However, the 5 V regulator circuit does operate and provide its output in the power saving state. 5. Reference clock The externally input clock signal must be free of chattering and other noise. The input circuit does have hysteresis, but if problems occur, the clock signal must be input through a capacitor or other noise reduction circuit. If the IC is set to the start state with no reference clock input, and if the constraint protection circuit is operated, after the motor rotates a certain amount, the drive will be turned off. However, if the constraint protection circuit is not operated, and furthermore, if reverse control mode is selected during braking, the motor will run backwards at increasing speed. A workaround will be required in this case. (This problem occurs because the constraint protection circuit oscillator signal is used for clock cutoff protection.) 6. PWM frequency The PWM frequency is determined by the capacitor C (F) connected to the PWM pin. fPW 1/(15000 x C) If an 1800 pF capacitor is used, the frequency will be about 37 kHz. If the PWM frequency is too low, the motor will emit audible switching noise, and if it is too high, the power loss will increase. A frequency in the range 15 to 50 kHz is desirable. The capacitor ground must be connected as close as possible to the IC control block ground (the GND1 pin) to minimize the influence of the output on this circuit.
No. 6201-12/14
LB1876 7. Hall sensor input signals Input signals with amplitudes greater than the input circuit hysteresis (42 mV maximum) must be provided to the Hall inputs. Input amplitudes of over 100 mV are desirable to minimize the influence of noise. If the output waveform is disturbed by noise (at phase switching), insert capacitors across the input to prevent this. 8. FG input signal Normally, one of the Hall sensor signals is input as an FG signal. If noise on the FG input is a problem, insert either a capacitor or a filter consisting of a capacitor and a resistor. Although it is possible to exclude noise from the FG signal by inserting a capacitor between the FGFIL pin and ground, if this pin's waveform is smoothed excessively, the circuit may not be able to operate normally. Therefore, if a capacitor is used here, its value must be held to under 2200 pF. If the position of the capacitor's ground lead is inappropriate, problems due to noise may become more likely to occur. Select the position carefully. 9. Constraint protection circuit This IC includes a built-in constraint protection circuit to protect the IC and the motor during motor constraint. In the start state, when the LD output is high for a fixed period (the unlocked state), the lower side transistor turns off. The time is set by the capacitor connected to the CSD pin. Set time (seconds) 120 x C (F) If a 0.068 F capacitor is used, the protection time will be about 8 seconds. The set time must have a value that provides an adequate margin relative to the motor start time. The protection circuit does not operate during braking implemented by switching the clock frequency. Either switch to the stop state or turn off the power and restart to clear the constraint protection state. Since the CSD pin also functions as the initial reset pulse generation pin, if connected to ground the logic circuits will be reset and speed control operation will not be possible. Therefore, if constraint protection is not used, connect CSD to ground through a resistor of about 220 k and a capacitor of about 4700 pF in parallel. 10. Phase lock signal (1) Phase lock range Since this IC does not have a counter in the speed control system, the speed error range in the phase locked state cannot be determined solely by the IC's characteristics. (This is because of the influence of the acceleration of the changes in the FG frequency.) If it is necessary to stipulate this for the motor, it will be necessary to measure this with the actual motor. Since it is easier for speed errors to occur in the state where the FG acceleration is large, the largest speed errors are thought to occur during lock pull-in at startup and when unlocked due to clock frequency switching. (2) Phase lock signal mask function When the LDSEL pin is set high or left open, transient lock signals (short low-level periods on the LD output) is masked. This function masks short low-level periods due to hunting during pull-in and allows a stable lock signal to be output. However, the lock signal is delayed by amount of masking time. When the LDSEL pin is set low, transient unlock signals (short high-level periods on the LD output) is masked. This function prevents short period high-level signals from being output. The mask time is set with the capacitor connected between the CLD pin and ground. Mask time (seconds) 0.9 x C (F) A mask time of about 90 ms can be set by using a capacitor of about 0.1 F. If complete masking is required, the mask time must be set large enough to provide ample margin. If masking is not required, leave the CLD pin open.
No. 6201-13/14
LB1876 11. Power supply stabilization Since this IC provides a large output current and adopts a switching drive technique, it can easily disrupt the power supply line voltage. Therefore, capacitors with ample capacitance must be inserted between the VCC pins and ground. If reverse control mode is selected during braking, the circuit will return current to the power supply. This means that the power supply lines are even more susceptible to disruption. Since the power supply is most easily influenced during lock pull-in at high motor speeds, this case requires particular care. Select capacitor values that are fully adequate for this case. If diodes are inserted in the power supply lines to prevent damage if the power supply is connected with reverse polarity, the power supply voltage will be even more susceptible to disruption, and even larger capacitors must be used. 12. VREG stabilization Insert a capacitor of at least 0.1 F to stabilize VREG, which is the control circuit power supply. The capacitor ground must be connected as close as possible to the IC control block ground (the GND1 pin). 13. Error amplifier circuit components Locate the error amplifier components as close to the IC as possible to minimize the influence of noise on this circuit. Locate this circuit as far from the motor as possible.
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of June, 2002. Specifications and information herein are subject to change without notice. PS No. 6201-14/14

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